Performing system tasks at power-off using system management interrupt
US5511204A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Sep 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. Prior to causing the power supply to cease providing regulated power to the CPU, the power management processor interrupts the CPU via a system management interrupt. Responsive to being interrupted via the system management interrupt, the CPU performs tasks associated with the power supply imminently ceasing to provide regulated power to the CPU. Such tasks include writing data to non-volatile memory and refreshing an alarm value in the power management processor. The CPU can extend the period of time before the power management processor causes the power supply to cease providing regulated power to the CPU while the CPU performs the necessary tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.