Zero latency overhead self-timed iterative logic structure and method
US5513132A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of cascaded domino logic gates which are pipelined without intervening latches for memory storage. The memory storage function of the conventional latches being provided by the third logic phase. The novel approach requires that the functional inputs to this system have strictly monotonic transitions during the logic evaluation phase, and requires that the precharge signal must be active during only the precharge phase. Embodiments of the pipelined system according to the invention, are structured so that the output of the pipeline are fed back to the input of the pipeline to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic. The logic ring circulates data until the entire computation is complete. A method for using the logic structure is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.