Built-in self-test tri-state architecture
US5513190A · kind A · utility
17Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1991 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Oct 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit architecture for driving a tri-state bus in a logic circuit that uses a built-in self-test (BIST) mechanism. The architecture includes tri-state drivers which have circuitry to inhibit other drivers from driving the bus when another driver is driving the bus. The architecture includes circuitry to pullup the bus or to allow the bus to retain the last state it was driven to when none of the drivers is driving the bus. This circuitry also drives the bus to a known state during testing of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.