Watchdog timer for computer system reset
US5513319A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1995 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Jun 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A watchdog timer circuit of the present invention monitors a computer system (S) during diagnostic testing and resets the system when it is nonfunctioning. A real-time clock (RTC) (21), programmed by a central processing unit (CPU) (29) to run for a period of time, produces a reset signal after the period of time elapses. Typically this time period relates to a diagnostic program being run. The reset signal serves as an input to reset circuitry (28) which immediately transmits a nonmaskable interrupt (NMI) to the CPU (29) and, after a delay period, transmits a hardware reset signal to the CPU (29). When functioning properly, the CPU (29) prepares for the hardware reset signal that is produced by the reset circuitry (28) and avoids being reset by the hardware reset signal. However, when the CPU (29) is not functioning properly, the hardware reset signal resets the CPU (29). Additional circuitry stores information regarding where the system (S) failed during the diagnostic testing and retrieves such information for the user upon reset. An additional feature resets all of the components within the system (S) upon a CPU (29) reset via power reset circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.