Error condition detector for handling interrupt in integrated circuits having multiple processors
US5513346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1993 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Oct 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt processor controller (IPC) through which all interprocessor interrupts are routed in a complex integrated circuit. For processors which receive external interrupts, the interrupt processor controller may receive those interrupts and route those as well to the particular processor. The IPC includes interrupt routing logic which determines when a subsequent interrupt will cause an error condition with a previously instigated interrupt that has not been cleared. When such a condition occurs, a bit is set in an error detect register that is coupled to the interrupt routing logic. All of the bits of the error detect register are logically OR'ed, the output of which is routed to a single dedicated pin for indicating an interrupt error condition has occurred. This pin may have its signal routed back into the complex integrated circuit for signaling a trap handler or some other mechanism that an interrupt error condition has occurred. During debug, the error detect register may be checked to determine which bit has been set wherein each bit corresponds to a single interprocessor interrupt channel. Thus, the location of the interrupt error in the executing code can be determine…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.