Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
US5513377A · kind A · utility
85Cited by
12References
3Claims
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Key dates
| Filing date | Jun 17, 1994 |
| Grant date | Apr 30, 1996 |
| Priority date | — |
| Expiry date | Jun 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.