Method of producing a semiconductor memory device having thin film transistor load

US5514615A · kind A · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Taiji Ema · Inabe, JP
• Kazuo Itabashi · Kawasaki, JP

Key dates

• Filing date: May 15, 1995
• Grant date: May 7, 1996
• Expiry date: May 15, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/125

Abstract

A method of producing a memory cell on a semiconductor substrate. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors. A field insulator layer is formed on the semiconductor substrate. A gate insulator layer is formed above the field insulator layer. A gate electrode of a driver transistor is produced by forming a first conductor layer above the gate insulator layer. Impurity regions are formed in the semiconductor substrate using the field insulator layer and the first conductor layer as masks. A first insulator layer is then formed. Source, drain and channel regions of a thin film transistor load are produced by forming a second conductor layer and injecting impurities into the second conductor layer. A second insulator layer is formed above the second conductor layer. A contact hole is formed to extend from the second insulator layer, through the second conductor layer, and to the first conductor layer. A storage electrode of a memory capacitor is produced by forming a third conductor layer which makes contact with the first conductor layer and the second conductor layer through the contact hole. A …