Addressing modes for a dynamic single bit per cell to multiple bit per cell memory
US5515317A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Jun 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory locations and the physical addresses when operating in the standard cell mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.