Variable-size first in first out memory with data manipulation capabilities
US5515329A · kind A · utility
9Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Nov 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.