Timeslot interleaving delay compensation (bonding) mechanism for time division multiplexed digital communication network
US5515371A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Oct 26, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a time division multiplexed digital communication network through which time division multiplexed data signals are routed over respectively different transmission paths of the network, the paths having respectively different transmission delays, to a bonding receiver at a destination end of the network, the bonding receiver including a digital signal processor for controlling the operation of the bonding receiver, bonding compensation that is normally carried out entirely by the digital signal processor is transferred from the digital signal processor to an auxiliary delay path, which is coupled to the receive path from the network. The auxiliary delay path is controlled by the direct memory access (DMA) functionality of the digital signal processor to transfer selected data time slots through the auxiliary delay path. The output of the auxiliary delay path is controllably multiplexed with undelayed time slots, so as to be re-injected into the receive path and time division multiplex aligned with and synchronously interleaved with the slower channel's time slots upstream of the input of the digital signal processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.