Apparatus and method for clock alignment and switching
US5515403A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Jun 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path having a programmable delay value, which delays it and produces a first output timing signal. A second delay path receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of phase relationship therebetween. The circuitry further provides for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.