Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle
US5515506A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1994 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Aug 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parity generation circuit for an internal cache memory of a computer processor. The parity generation circuit generates parity for both reading and writing during execution of a single processor instruction. The parity generation circuit saves processor circuitry by sharing one parity logic tree for both reading and writing. During one clock phase, a multiplexer routes data to the memory through the parity logic tree and a demultiplexer routes parity from the parity logic tree to the memory. During a second clock phase, the multiplexer routes data from the memory through the parity logic tree and the demultiplexer routes parity from the parity logic tree to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.