Multiple width data bus for a microsequencer bus controller system
US5515507A · kind A · utility
8Cited by
9References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | May 7, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.