Method of producing static random access memory device having thin film transister loads

US5516715A · kind A · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Kazuo Itabashi · Kawasaki, JP
• Taiji Ema · Inabe, JP

Key dates

• Filing date: Oct 27, 1994
• Grant date: May 14, 1996
• Expiry date: Oct 27, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

A method of producing a semiconductor memory cell. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors. The method includes (a) forming a field insulator layer on a semiconductor substrate, (b) forming a gate insulator layer, (c) forming a gate electrode of a driver transistor by forming and patterning a first conductor layer, (d) forming a first insulator layer on the first conductor layer after impurity regions are formed in the semiconductor substrate, (e) forming and patterning a second conductor layer on the first insulator layer, (f) forming a second insulator layer on the second conductor layer, (g) forming and patterning a third conductor layer on the second insulator layer, (h) forming a third insulator layer on the third conductor layer, (i) forming a contact hole which extends from the top surface of the third insulator layer to the top surface of the first conductor layer, the contact hole extending through the second conductor layer and the third conductor layer, and (j) forming a fourth conductor layer which extends into the cont…