Method of manufacturing local interconnection for semiconductors
US5516726A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Nov 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process, compatible with bipolar and CMOS processes, for making local interconnection of adjacent devices on a semiconductor substrate is disclosed. An electrically insulating etch stop layer is deposited over the semiconductor substrate including the device contact openings. A conductive layer is deposited over the etch stop layer. The conductive layer is patterned into a local interconnect by use of resist patterning and subtractive etching, stopping on the etch stop layer. By thermal activation, the conductive pattern and the underlying insulating material interact to become a single electrically conductive layer. This layer also establishes electrical contact to the devices thus completing the formation of the local interconnection of the devices on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.