Semiconductor device having multi-level wiring structure
US5517042A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Dec 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to the invention includes a first layer including first and second device regions, in which semiconductor devices are formed; and a second layer including a signal line region, a first power supply region, which is one selected between power source and ground and a second power supply region which is the remaining of the power source and ground, the second power supply region being horizontally positioned between the signal line and first power supply regions. The first device region is positioned under both said first and second power supply regions. The second device region is positioned under the signal line region and the second power supply region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.