Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal
US5517109A · kind A · utility
18Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1995 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Jan 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) includes circuitry for generating a clock signal during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector. In test mode, an input test clock signal bypasses the skew corrector via a clock signal source selector. The clock signal source selector is controlled automatically by a mode detector that responds to the input clock signals to determine the mode of operation of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.