Sample and hold circuit
US5517140A · kind A · utility
7Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1995 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Apr 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a non-inverted input terminal of the operational amplifier and a signal ground so that the ringing cancel circuit is connected in parallel with the hold capacitor. The ringing cancel circuit is made up of a resistance and a capacitor connected in series with each other. With this arrangement, a high-speed, highly accurate, low power consumptive sample and hold circuit can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.