Gain linearity correction circuit for MOS circuits
US5517149A · kind A · utility
1Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Jun 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.