Fast multiply-add instruction sequence in a pipeline floating-point processor
US5517438A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Jul 20, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.