Phase locked loop with reduced phase noise
US5517534A · kind A · utility
35Cited by
10References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An accumulator-based phase locked loop reduces phase noise by shifting the energy of the phase noise to higher frequencies. A second accumulator is inserted between a first accumulator and a pulse generator to integrate a phase error from the first accumulator referenced to a clock signal. The output of the pulse generator is an approximation frequency signal that is compared with a comparable frequency signal derived from a reference signal to produce an error signal to control the frequency of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.