System bus control system for multiprocessor system
US5517625A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1993 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Oct 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system bus control system for a system has a plurality of first modules and at least one second module. The first and second modules are connected together via a system bus which is controlled by an arbiter receiving requests to use the system bus from the first and second modules. Each of the first modules includes a lock control signal supervising unit, a lock control signal outputting unit, a command outputting unit and a response receiving unit. Each of the second modules includes a lock control signal supervising unit, a source module information storing unit, a command receiving unit and a response outputting unit. The lock control is controlled by the first and second modules rather than the arbiter, which permits one of the first and second modules to use the system bus if the system bus is idle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.