Multiprocessor system with distributed memory
US5517662A · kind A · utility
69Cited by
18References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Nov 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processors is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviors in the protocol when message packets depart or when they arrive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.