Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
US5518942A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1995 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Feb 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/00
Abstract
A method of manufacturing a flash EPROM cell is disclosed. A flash EPROM gate stack (114) is formed on p-type silicon substrate (100) having tunnel oxide (102) thereon. The gate stack (114) includes a polysilicon floating gate (106), an intergate dielectric (108), and a control gate (116). The substrate (100) includes a source region (120), a channel (122) and a drain region (118) therebetween. A source implant mask (124) is created that covers at least the drain region (118) and leaves the source region (120) exposed. Large angle ion implantation is used to implant a source dopant into the source region (120) below the floating gate (106) of the gate stack (114). The source implant mask (124) is stripped and the source and drain regions (118 and 120) are doped with a source/drain implant by ion implantation at an implant angle of approximately zero degrees (.about.0.degree.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.