Elevated voltage level I.sub.DDQ failure testing of integrated circuits
US5519333A · kind A · utility
26Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1994 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Sep 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.