Electronic tester for testing I.sub.ddq in an integrated circuit chip
US5519335A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1995 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Mar 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic tester, for testing I.sub.ddq in an integrated circuit chip, comprises: 1) a first power supply, having a large current capacity, which sends current to the chip through a first diode; 2) a second power supply, having a current sensor and a small current capacity which is substantially less than the large current capacity, which sends current to the chip through a second diode which is in parallel with the first diode; and 3) a control module which sends test vectors to the chip during a series of spaced apart T.sub.A time intervals, and sends control signals to at least one of the power supplies which indicate when the T.sub.A time intervals occur. In response to the control signals, the one power supply generates a first output voltage during the T.sub.A time intervals which forward biases said first diode and reverse biases said second diode; and it also generates a second output voltage between the T.sub.A time intervals which forward biases the second diode and reverse biases the first diode so long as the small current capacity is not exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.