Method of dividing a pipelined stage into two stages in a computer-aided design system
US5519626A · kind A · utility
1Cited by
6References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1993 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Jul 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, practiced in a CAD system, of automatically dividing a pipeline stage into two. A designer specifies a desired signal processing time for division of the stage. The CAD system automatically identifies circuit locations that meet the specified signal processing time and divides the stage at those points, providing new netlists for the new stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.