Adapter for the connection to a clear-channel telecommunication network
US5519737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1993 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Apr 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.