Processor communications bus having address lines selecting different storage locations based on selected control lines
US5519876A · kind A · utility
5Cited by
13References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | May 21, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.