Process of fabricating memory cell with a switching transistor and a trench-stacked capacitor coupled in series
US5521111A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | May 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A memory cell is implemented by a series combination of a field effect transistor and a trench-stacked type storage capacitor, and an accumulating electrode is held in contact with a source region of the field effect transistor through an extremely narrow gap between a side spacer on a gate electrode of the field effect transistor and an isolation layer extending along a primary trench nested with the source region, wherein the side spacer is formed from a deposited doped polysilicon film and the isolation layer is formed by thermally oxidizing a wall portion of the primary trench so that the extremely narrow gap is defined without lithographic techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.