Precision dicing of silicon chips from a wafer
US5521125A · kind A · utility
45Cited by
19References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Oct 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer design and dicing technique for creating semiconductor chips from wafers. A succession of oxide layers are deposited in first and second regions of a surface of a silicon substrate. The regions are separated by a street having no oxide layers therein, and the successive oxide layers form a vertical wall with a surface normal to the surface of the silicon substrate. A shock-absorbent material is deposited in the street, forming a concave meniscus therein. The shock-absorbent material retards the trajectories of silicon particles set into motion when the wafer is diced into chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.