Low-capacitance, plugged antifuse and method of manufacture therefor
US5521440A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | May 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An antifuse structure in an integrated circuit is provided. The antifuse structure has a first metal interconnection line and a first insulating layer over the first metal interconnection line. The first insulating layer has a via exposing a top surface of the first metal interconnection line. In the first aperture a metal plug contacts the first metal interconnection layer and has a top surface substantially coplanar with a top surface of the first insulating layer. A metal pad contacts and covers the top surface of the metal plug. The metal pad should be formed by a viscous barrier metal, such as TiW, to smooth the surface of the metal plug. A second insulating layer, relatively thin with respect to said first insulating layer, covers the metal pad and has an aperture exposing a top surface of the metal pad. A programming layer deposited over the second insulating layer and into the aperture contacts the top surface of metal pad. A second metal interconnection line rests on the programming layer. In an alternative embodiment the locations of the second insulating layer and the programming layer are reversed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.