Signal controlled phase shifter
US5521499A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1992 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.