High speed analog signal sampling system
US5521599A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Oct 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an outp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.