Non-volatile semiconductor memory device allowing fast verifying operation
US5521864A · kind A · utility
36Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1995 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Feb 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.