Semiconductor memory device having a coincidence detection circuit and its test method
US5521870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Dec 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory blocks, a write circuit for writing data into the memory blocks, a read circuit for reading data from the memory blocks, a plurality of serial registers, each of which is connected to the corresponding memory block to output serially a plurality of data read from the memory block, a plurality of switches, each of which is arranged between two adjacent ones of the serial registers to connect the serial registers in series, and a coincidence detection circuit for detecting a coincidence of data outputted from a final serial register arranged at a final end of the serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.