Method and system for invalidating instructions utilizing validity and write delay flags in parallel processing apparatus
US5522084A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Sep 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing predetermined functions, and a decode state decoding the fetched instructions to issue parallel-processable instructions to related functional units. The decode stage includes a decoder determining whether a branch instruction is included in the received instructions and whether a branch is generated according to the branch instruction. The decoder links a write delaying flag indicating whether the instruction is after a branch instruction and a validity flag indicating whether the instruction is valid to the instruction on issuing the instruction to a functional unit. The functional unit includes an execution stage executing an instruction and a write back stage changing a machine state according to the result of execution in the execution stage. The superscalar-type processor comprises a control circuit forbidding changing of the machine state by a write back stage when a branch is generated according to the branch instruction. The control circuit sets the write back stage in a state of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.