Arithmetic engine with dual multiplier accumulator devices
US5522085A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1995 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Feb 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.