Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus
US5522088A · kind A · utility
21Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1994 |
| Grant date | May 28, 1996 |
| Priority date | — |
| Expiry date | Jun 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.