Semiconductor device having laminated tight and coarse insulating layers
US5523616A · kind A · utility
487Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 25, 1994 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Oct 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having a passivation layer, the passivation layer includes a laminated configuration formed by a plurality of tight insulating layers and a plurality of coarse insulating layers alternating with the tight insulating layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.