High speed, low power macrocell
US5523706A · kind A · utility
7Cited by
20References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1995 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Mar 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.