Fast, low power exclusive or circuit
US5523707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a "tree" configuration by providing a "push-pull" XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to "push" the output to a next stage. Additional transistors are provided to help "pull" internal nodes to the operating voltage but are not logically functional transistors. Further, input connections to the logical transistors are such as to eliminate unnecessary delay between like stages, when configured as a "tree".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.