Symmetric clock system for a data processing system including dynamically switchable frequency divider
US5524035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1995 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Aug 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.