Patent · US Expired

Circuit configuration for generating even-numbered duty factors

US5524037A · kind A · utility

4Cited by

5References

2Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Gunter Donig · Poing, DE
Edmund Goetz · Dachau, DE
Helmut Herrmann · Hersbruck, DE

Key dates

Filing date	Dec 1, 1994
Grant date	Jun 4, 1996
Priority date	—
Expiry date	Dec 1, 2014

Classification

Technology area (CPC H)Electricity
CPC primaryH03K23/505
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.