Redundancy removal using quasi-algebraic methods
US5524082A · kind A · utility
24Cited by
9References
22Claims
0Family size
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Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.