Controlling data transfer between two microprocessors by receiving input signals to cease its data output and detect incoming data for reception and outputting data thereafter
US5524237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1992 |
| Grant date | Jun 4, 1996 |
| Priority date | — |
| Expiry date | Dec 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A microprocessor communication system couples two microprocessors over a bus comprising a bidirectional data line, a bidirectional sync line and a pair of clock lines. A toggled clock signal serves as a control signal. Each microprocessor outputs data to the data and sync lines and monitors its incoming clock line. When a toggled clock signal is sensed, the receiving microprocessor, when its priorities permit, takes control of the bus and stops outputting data to the data and sync lines. It then detects the incoming data and when incoming data reception is completed, the microprocessor outputs new information to the data and sync lines and toggles its output clock line to signal to the other microprocessor that control of the bus has been relinquished. With the system, the microprocessors operate without the constraints of predetermined time intervals in which to output data or to receive data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.