Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers

US5524250A · kind A · utility

Assignee

• Silicon Graphics, Inc. · US

Inventors

• Greg Chesson · Palo Alto, US
• In Whan CHOI · Mountain View, US
• Yuh-wen Lin · San Jose, US
• Jeannine Marie Smith · Menlo Park, US
• Daniel Yau · Los Altos, US
• Desmond W. Young · Campbell, US

Key dates

• Filing date: Dec 23, 1994
• Grant date: Jun 4, 1996
• Expiry date: Dec 23, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L69/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.