Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations
US5526278A · kind A · utility
62Cited by
7References
20Claims
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Key dates
| Filing date | Jun 20, 1995 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Jun 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system, in which the relative physical placement of configurable logic blocks, signal routing networks, and clock distribution trees of the FPGA implementation is preserved on the mask programmable logic cell (MPLC) substrate after the conversion process is completed. By constraining the physical placement of corresponding structures on the MPLC substrate at the network level of the MPLC implementation, the relative signal and clock delays presented during the FPGA implementation are substantially maintained in the MPLC implementation, thereby assuring functional equivalence between the FPGA and MPLC implementations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.