Apparatus for detecting undefined states of a finite state machine (FSM) and resetting the FSM upon detection
US5526486A · kind A · utility
6Cited by
7References
9Claims
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Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.