Memory addressing device
US5526513A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1994 |
| Grant date | Jun 11, 1996 |
| Priority date | — |
| Expiry date | Nov 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory addressing device for data processing apparatus addresses in sequence and in a burst a series of memory locations in a single addressing period of a central processing unit. The device comprises enabling circuits to set a central processing unit (CPU) to a burst transfer cycle and to keep a memory control unit (MCU) in a waiting state during the burst transfer. An address generator circuit is capable of generating in sequence a series of memory address codes to address a series of locations in the memory (RAM) during the burst transfer cycle. A multiplexer circuit sends to the memory either the address code of the address generator or that of the memory control unit during the burst cycles and the normal cycles respectively. The device is particularly suitable for use in personal computers with high data transfer rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.